1. Field of the Invention
The present invention relates to decoding/demodulating pulse width modulated signals.
2. Description of the Related Art
A pulse width modulated (PWM) signal is a digital signal that is modulated by duty cycle to encode information. The duty cycle of the PWM signal is defined as a percentage of a given cycle time of the PWM signal at which the PWM signal is in a high state. For example, if a given cycle of the PWM signal has a duty cycle of 40%, the PWM signal is in the high state for 40% of the given cycle, and in the low state for the other 60% of the given cycle. The PWM signal can include variations in duty cycle between different cycles of the PWM signal, with the variations in duty cycle corresponding to an encoding of information. For example, a first duty cycle in the PWM signal can represent a first digital logic state, and a second duty cycle in the PWM signal can represent a second digital logic state. For example, the first duty cycle of the PWM signal can be a 40% duty cycle that represents a digital logic state of zero, and the second duty cycle of the PWM signal can be a 60% duty cycle that represents a digital logic state of one. Therefore, if the PWM signal includes two successive cycles that have the 40% duty cycle followed by the 60% duty cycle, these two successive cycles of the PWM signal will decode to the digital logic state of zero followed by the digital logic state of one. Also, the PWM signal can vary in frequency, which corresponds to a change in the period, i.e., duration, of different cycles of the PWM signal. Decoding of the PWM signal is necessary to obtain the information represented by the modulation of the duty cycle with the PWM signal. It is within this context that the present invention arises.